This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-VVCC operation.

The SN74LVC2G00 device performs the Boolean function Y = A × B orY = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA =
    25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power
    Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model

Part number立即下单Technology FamilyVCC(Min)(V)VCC(Max)(V)Channels(#)Inputs per channelIOL(Max)(mA)IOH(Max)(mA)Input typeOutput typeFeaturesRatingData rate(Max)(Mbps)Operating temperature range(C)Package size: mm2:W x L (PKG)Package Group
SN74LVC2G00立即下单LVC  1.65  5.5  2  2  32  -32  Standard CMOS  Push-Pull  Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)  
Catalog  100  -40 to 125  8DSBGA: 3 mm2: 2.25 x 1.25 (DSBGA|8)
8SM8: 12 mm2: 4 x 2.95 (SM8|8)
8VSSOP: 6 mm2: 3.1 x 2 (VSSOP|8)  
DSBGA|8
SM8|8
VSSOP|8  

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