The DS90CR481 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low VoltageDifferential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel withthe data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input dataare sampled and transmitted. The DS90CR482 receiver converts the LVDS data streams back into 48bits of LVCMOS/TTL data. At a transmit clock frequency of 112MHz, 48 bits of TTL data aretransmitted at a rate of 672Mbps per LVDS data channel. Using a 112MHz clock, the data throughputis 5.38Gbit/s (672Mbytes/s). At a transmit clock frequency of 112MHz, 48 bits of TTL data aretransmitted at a rate of 672Mbps per LVDS data channel. Using a 66MHz clock, the data throughput is3.168Gbit/s (396Mbytes/s).

The multiplexing of data lines provides a substantial cable reduction. Long distanceparallel single-ended buses typically require a ground wire per active signal (and have verylimited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1clock pair and a minimum of one ground) are needed. This provides an 80% reduction in cable width,which provides a system cost savings, reduces connector physical size and cost, and reducesshielding requirements due to the cables' smaller form factor.

The 48 CMOS/TTL inputs can support a variety of signal combinations. For example, 6 8-bitwords or 5 9-bit (byte + parity) and 3 controls.

The DS90CR481/DS90CR482 chipset is improved over prior generations of Channel Linkdevices and offers higher bandwidth support and longer cable drive with three areas of enhancement.To increase bandwidth, the maximum clock rate is increased to 112 MHz and 8 serialized LVDS outputsare provided. Cable drive is enhanced with a user selectable pre-emphasis feature that providesadditional output current during transitions to counteract cable loading effects. Optional DCbalancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference).With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end ofthe cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew ofup to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+meters in length to be driven.

The chipset is an ideal means to solve EMI and cable size problems associated with wide,high speed TTL interfaces.

  • 3.168 Gbits/sec Bandwidthwith 66 MHz Clock
  • 5.376 Gbits/sec Bandwidth with 112 MHzClock
  • 65 - 112 MHz Input Clock Support
  • LVDS SER/DESReduces Cable and Connector Size
  • Pre-Emphasis Reduces Cable LoadingEffects
  • Optional DC Balance Encoding Reduces ISIDistortion
  • Cable Deskew of +/−1 LVDS Data Bit Time (up to 80 MHz ClockRate)
  • 5V Tolerant TxIN and Control Input Pins
  • Flow ThroughPinout for Easy PCB Design
  • +3.3V Supply Voltage
  • TransmitterRejects Cycle-to-Cycle Jitter
  • Conforms to ANSI/TIA/EIA-644-1995 LVDSStandard

All trademarks are the property of their respective owners.

Part number立即下单FunctionRatingOperating temperature range(C)Package GroupPackage size: mm2:W x L (PKG)
DS90CR482立即下单Deserializer  Catalog  -10 to 70  TQFP | 100  100TQFP: 256 mm2: 16 x 16 (TQFP | 100)  
DS90CR481无样片Serializer  Catalog  -10 to 70  TQFP | 100  100TQFP: 256 mm2: 16 x 16 (TQFP | 100)  

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